The present disclosure relates generally to the field of fabrication of semiconductor devices, and more specifically to a method of fabricating a fin type field effect transistor (FinFET) or portion thereof.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin-like field effect transistor (FinFET). A typical FinFET is fabricated with a thin ‘fin’ extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. It is beneficial to have a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow.
Additionally, various materials have been implemented for the gate electrode and gate dielectric in CMOS technology. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease. A gate last (or gate replacement) approach has been implemented to address concerns of high temperature processing on metal materials.
Therefore, what is desired is a method of fabricating FinFET devices in a gate last process.